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january 2008 rev 2 1/58 1 nand08gw3c2a nand16gw3c4a 8/16 gbit, 2112 byte page, 3 v supply, multilevel, mult iplane, nand flash memory features high density multilevel cell (mlc) flash memory ? up to 16 gbit memory array ? up to 512 mbit spare area ? cost-effective solutions for mass storage applications nand interface ? x 8 bus width ? multiplexed address/data supply voltage: v dd = 2.7 to 3.6 v page size: (2048 + 64 spare) bytes block size: (256k + 8k spare) bytes multiplane architecture ? array split into two independent planes ? program/erase operations can be performed on both planes at the same time page read/program ? random access: 60 s (max) ? sequential access: 25 ns (min) ? page program operation time: 800 s (typ) multipage program time (2 pages): 800 s (typ) fast block erase ? block erase time: 2.5 ms (typ) multiblock erase time (2 blocks): 2.5 ms (typ) status register electronic signature serial number option chip enable ?don?t care? data protection ? hardware program/erase locked during power transitions development tools ? error correction code models ? bad block management and wear leveling algorithm ? hw simulation models data integrity ? 10,000 program/erase cycles (with ecc) ? 10 years data retention ecopack ? packages available lga52 12 x 17 mm (n) tsop48 12 x 20 mm (n) www.numonyx.com
nand08gw3c2a, nand16gw3c2a 2/58 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 bad blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 inputs/outputs (i/o0-i/o7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 address latch enable (al) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3 command latch enable (cl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 chip enable (e 1 , e 2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5 read enable (r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6 write enable (w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7 write protect (wp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8 ready/busy (rb 1 , rb 2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.9 v dd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.10 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.4 data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.5 write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.6 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 read memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3 page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.4 page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
nand08gw3c2a, nand16gw3c2a 3/58 6.5 sequential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.6 random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.7 multiplane page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.8 block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.9 multiplane block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.10 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.11 read status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.11.1 write protection bit (sr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.11.2 p/e/r controller bit (sr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.11.3 error bit (sr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.12 sr5, sr4, sr3, sr2 and sr1 bits are reserved . . . . . . . . . . . . . . . . . . . 29 6.13 read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7 concurrent operations and ers on the nand16gw3c2a . . . . . . . . . 32 8 data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9 software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.1 bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.2 nand flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.3 garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.4 wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.5 hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.5.1 behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.5.2 ibis simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10 program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 38 11 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 12.1 ready/busy signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 52 12.2 data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
nand08gw3c2a, nand16gw3c2a 4/58 14 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
nand08gw3c2a, nand16gw3c2a 5/58 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. valid blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5. address insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6. address definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 7. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. status register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 9. electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 10. electronic signature byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 11. electronic signature byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 12. electronic signature byte 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 13. extended read status register commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 14. block failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 15. program and erase times and program erase endurance cycles . . . . . . . . . . . . . . . . . . . . 38 table 16. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 17. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 18. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 19. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 20. ac characteristics for command, address, data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 21. ac characteristics for operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 22. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data. . . . . 54 table 23. lga52 12 x 17 mm, 1 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 55 table 24. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 25. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
nand08gw3c2a, nand16gw3c2a 6/58 list of figures figure 1. logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. tsop48 connections for nand08gw3c2a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. tsop48 connections for nand16gw3c4a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. ulga52 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 6. memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7. read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 8. random data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 9. page program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 10. random data input during sequential data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 11. multiplane page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 12. block erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 13. multiplane block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 14. bad block management flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 15. garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 16. command latch ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 17. address latch ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 18. data input latch ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 19. sequential data output after read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 20. sequential data output after read ac waveforms (edo mode). . . . . . . . . . . . . . . . . . . . . 46 figure 21. read status register ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 figure 22. read electronic signature ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 23. page read operation ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 24. page program ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 25. block erase ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 26. reset ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 27. program/erase enable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 28. program/erase disable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 29. ready/busy ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 30. ready/busy load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 31. resistor value versus waveform timings for ready/busy signal. . . . . . . . . . . . . . . . . . . . . 53 figure 32. data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 33. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline . . . . . . . . . . . . 54 figure 34. lga52 12 x 17 mm, 1 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
nand08gw3c2a, nand16 gw3c2a description 7/58 1 description the nand08gw3c2a and nand16gw3c2a are multilevel cell (mlc) devices from the nand flash 2112-byte page family of non-volatile flash memories. the nand08gw3c2a and the nand16gw3c2a have a density of 8- and 16-gbit, respectively. the nand16gw3c2a is composed of two 8-gbit dice; each die can be accessed independently using two chip enable and two ready/busy signals. the devices operate from a 3 v vdd power supply. the address lines are multiplexed with the data input/output signals on a multiplexed x8 input/output bus. this interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint. each block can be programmed and erased over 10,000 cycles (with ecc on). the device also has hardware security features; a write protect pin is available to give hardware protection against program and erase operations. the devices feature an open-drain, ready/busy output that can be used to identify if the program/erase/read (p/e/r) controller is currently active. the use of an open-drain output allows the ready/busy pins of several memories to be connected to a single pull-up resistor. the memory array is split into 2 planes of 2048 blocks each. this multiplane architecture makes it possible to program 2 pages at a time (one in each plane) or to erase 2 blocks at a time (one in each plane), dividing by two the average program and erase times. the devices have the chip enable ?don?t care? feature, which allows code to be directly downloaded by a microcontroller, as chip enable transitions during the latency time do not stop the read operation. there is the option of a unique identifier (serial number), which allows the nand08gw3c2a and the nand16gw3c2a to be uniquely identified. it is subject to an nda (non-disclosure agreement) and is, therefore, not described in the datasheet. for more details of this option contact your nearest numonyx sales office. the devices are available in tsop48 (12 20 mm) and lga52 (12 x 17 x 0.65 mm) packages. to meet environmental requirements, numonyx offers the devices in ecopack ? packages. ecopack packages are lead-free. in compliance with jedec standard jesd97, the category of second level interconnect is marked on the package and on the inner box label. the maximum ratings related to soldering conditions are also marked on the inner box label. the devices are shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to ?1?. refer to the list of available part numbers and to table 24: ordering information scheme for information on how to order these options.
description nand08gw3c2a, nand16gw3c2a 8/58 figure 1. logic block diagram 1. e 2 and rb 2 are only present in the nand16gw3c4a. table 1. device summary part number density bus width page size block size memory array operatin g voltage (v dd ) timings package random access time (max) sequentia l access time (min) page program (typ) block erase (typ) nand08gw3 c2a 8gb x8 2048+ 64 bytes 256 k + 8 k bytes 128 pages x 4096 blocks 2.7 to 3.6 v 60 s 25 ns 800 s 2.5 ms tsop48 ulga52 nand16gw3 c4a (1) 16 gb 128 pages x 8192 blocks tsop48 ulga52 1. the nand16gw3c2a is composed of two 8-gbit dice. address register/counter command interface logic p/e/r controller high voltage generator buffers e 1 w ai13296b r y decoder page buffer nand flash memory array x decoder command register cl al rb 1 data register i/o wp e 2 rb 2
nand08gw3c2a, nand16 gw3c2a description 9/58 figure 2. logic diagram 1. e 2 and rb 2 are only present in the nand16gw3c4a. table 2. signal names signal function direction i/o0 - i/o7 data input/outputs (1) 1. on the lga52 package, each 8-gbit die is acce ssed and controlled via two sets of i/os and control signals. input/output cl command latch enable input al address latch enable input e 1 , e 2 chip enable (2) input r read enable input w write enable input wp write protect input rb 1 , rb 2 ready/busy (open drain output) (2) 2. e 2 and rb 2 are only present in the nand16gw3c4a. output v dd power supply power supply v ss ground ground nc no connection du do not use ai13632b i/o0 - i/o7 x8 v dd nand flash w v ss wp al cl e 1 r rb 1 e 2 rb 2
description nand08gw3c2a, nand16gw3c2a 10/58 figure 3. tsop48 connections for nand08gw3c2a i/o3 i/o2 i/o6 r rb nc i/o4 i/o7 ai13633 nand flash 12 1 13 24 25 36 37 48 e i/o1 nc nc nc nc nc nc nc wp w nc nc nc v ss v dd al nc nc cl nc i/o5 nc nc nc i/o0 nc nc nc nc v dd nc nc nc v ss nc nc nc nc nc
nand08gw3c2a, nand16 gw3c2a description 11/58 figure 4. tsop48 connections for nand16gw3c4a i/o3 i/o2 i/o6 r rb1 rb2 i/o4 i/o7 ai13169 nand flash 12 1 13 24 25 36 37 48 e1 i/o1 nc nc nc nc nc nc nc wp w nc nc nc v ss v dd al e2 nc cl nc i/o5 nc nc nc i/o0 nc nc nc nc nc v dd nc nc nc v ss nc nc nc nc
description nand08gw3c2a, nand16gw3c2a 12/58 figure 5. ulga52 connections 1. on the lga52 package, each 8-gbit die is accessed and controlled via two sets of signals. ai13634 nc od oc ob al 1 oa 8 7 6 5 4 3 2 1 i/o0 2 of oe nc i/o1 2 i/o2 2 nc nc 0 nc nc nc nc nc nc nc nc nc nc a b c d e f g h j k l m n w 2 v ss al 2 i/o1 1 i/o3 1 v ss wp 1 cl 1 cl 2 i/o0 1 i/o3 2 i/o2 1 w 1 i/o4 1 v ss i/o6 1 e 1 e 2 rb 1 wp 2 v dd v ss i/o7 1 i/o5 1 v dd r 2 nc i/o7 2 nc i/o6 2 i/o5 2 rb 2 r 1 i/o4 2
nand08gw3c2a, nand16gw3c2a memory array organization 13/58 2 memory array organization the memory array is comprised of nand structures where 32 cells are connected in series. the memory array is organized in blocks where each block contains 128 pages. the array is split into two areas, the main area and the spare area. the main area of the array is used to store data, whereas the spare area is typically used to store software flags or bad block identification. the pages are split into a 2048-byte main area and a spare area of 64 bytes. refer to figure 6: memory array organization . 2.1 bad blocks the nand08gw3c2a and nand16gw3c2a devices may contain bad blocks, where the reliability of blocks that contai n one or more invalid bits is not guaranteed. additional bad blocks may develop during the lifetime of the device. the bad block information is written prior to shipping (refer to section 9.1: bad block management for more details). table 3: valid blocks shows the minimum number of valid blocks in each device. the values shown include both the bad blocks that are present when the device is shipped and the bad blocks that could develop later on. these blocks need to be managed using bad blocks management and block replacement (refer to section 9: software algorithms ). table 3. valid blocks (1) 1. the nand16gw3c4a is composed of two 8-gbit dice. the minimum number of valid blocks is 4096 for each die. density of device minimum maximum 8 gbits 4016 4096 16 gbits 8032 8192
memory array organization nand08gw3c2a, nand16gw3c2a 14/58 figure 6. memory array organization ai13170 x8 bus width plane = 2048 blocks block = 128 pages page = 2112 bytes (2,048 + 64) 2,048 bytes 2048 bytes 64 bytes block 64 bytes page page buffer, 2112 bytes main area 2,048 bytes 2048 bytes spare area 64 bytes 8 bits 64 bytes 8 bits page buffer, 2112 bytes main area spare area 2 page buffer, 2x 2112 bytes first plane second plane
nand08gw3c2a, nand16gw 3c2a signal descriptions 15/58 3 signal descriptions see figure 1: logic block diagram , and table 2: signal names , for a brief overview of the signals connected to this device. 3.1 inputs/outputs (i/o0-i/o7) input/outputs 0 to 7 are used to input the selected address, output the data during a read operation, or input a command or data during a write operation. the inputs are latched on the rising edge of write enable. i/o0-i/o7 are left floating when the device is deselected or the outputs are disabled. 3.2 address latch enable (al) the address latch enable activates the latching of the address inputs in the command interface. when al is high, the inputs are latched on the rising edge of write enable. 3.3 command latch enable (cl) the command latch enable activates the latching of the command inputs in the command interface. when cl is high, the inputs are latched on the rising edge of write enable. 3.4 chip enable (e 1 , e 2 ) the chip enable input activates the memory control logic, input buffers, decoders and sense amplifiers. when chip enable is low, v il , the device is selected. if chip enable goes high, v ih , while the device is busy, the device remains selected and does not go into standby mode. e 2 is only available on the nand16gw3c4a. 3.5 read enable (r ) the read enable pin, r , controls the sequential data output during read operations. data is valid t rlqv after the falling edge of r . the falling edge of r also increments the internal column address co unter by one. 3.6 write enable (w ) the write enable input, w , controls writing to the command interface, input address and data latches. both addresses and data are latched on the rising edge of write enable. during power-up and power-down a recovery time of 10 s (min) is required before the command interface is ready to accept a command. it is recommended to keep write enable high during the recovery time.
signal descriptions nand08g w3c2a, nand16gw3c2a 16/58 3.7 write protect (wp ) the write protect pin is an input that gives a hardware protection against unwanted program or erase operations. when write protect is low, v il , the device does not accept any program or erase operations. it is recommended to keep the write protect pin low, v il , during power-up and power-down. 3.8 ready/busy (rb 1 , rb 2 ) the ready/busy output, rb , is an open-drain output that can be used to identify if the p/e/r controller is currently active. when ready/busy is low, v ol , a read, program or erase operation is in progress. when the operation completes, ready/busy goes high, v oh . the use of an open-drain output allows the ready/busy pins from several memories to be connected to a single pull-up resistor. a low will then indicate that one, or more, of the memories is busy. during power-up and power-down a minimum recovery time of 10 s is required before the command interface is ready to accept a command. during this period the ready/busy signal is low, v ol . rb 2 is only available on the nand16gw3c4a. refer to section 12.1: ready/busy signal electrical characteristics for details on how to calculate the value of the pull-up resistor. 3.9 v dd supply voltage v dd provides the power supply to the internal core of the memory device. it is the main power supply for operations (read, program and erase). 3.10 v ss ground ground, v ss, is the reference for the power supply. it must be connected to the system ground.
nand08gw3c2a, nand16 gw3c2a bus operations 17/58 4 bus operations there are six standard bus operations that control the memory. each of these is described in this section. see the summary in table 4: bus operations . typically, glitches of less than 5 ns on ch ip enable, write enable and read enable are ignored by the memory and do not affect bus operations. 4.1 command input command input bus operations are used to give commands to the memory. commands are accepted when chip enable is low, command latch enable is high, address latch enable is low and read enable is high. they are latched on the rising edge of the write enable signal. only i/o0 to i/o7 are used to input commands. see figure 16 and ta b l e 2 0 for details of the timings requirements. 4.2 address input address input bus operations are used to input the memory addresses. five bus cycles are required to input the addresses (refer to table 5: address insertion ). the addresses are accepted when chip enable is low, address latch enable is high, command latch enable is low and read enable is high. they are latched on the rising edge of the write enable signal. only i/o0 to i/o7 are used to input addresses. see figure 17 and ta b l e 2 0 for details of the timings requirements. 4.3 data input data input bus operations are used to input the data to be programmed. data is only accepted when chip enable is low, address latch enable is low, command latch enable is low and read enable is high. the data is latched on the rising edge of the write enable signal. the data is input sequentially using the write enable signal. see figure 18 and ta b l e 2 0 for details of the timing requirements. 4.4 data output data output bus operations are used to read: the data in the memory array, the status register, the electronic signature and the unique identifier. data is output when chip enable is low, writ e enable is high, address latch enable is low, and command latch enable is low. the data is output sequentially using the read enable signal. if the read enable pulse frequency is lower then 33 mhz (t rlrl higher than 30 ns), the output data is latched on the rising edge of read enable signal (see figure 19 ).
bus operations nand08gw3c2a, nand16gw3c2a 18/58 for higher frequencies (t rlrl lower than 30 ns), the extended data out (edo) mode must be considered. in this mode, data output is valid on the input/output bus for a time of t rlqx after the falling edge of re ad enable signal (see figure 20 ). see ta bl e 2 1 for details on the timings requirements. 4.5 write protect write protect bus operations are used to pr otect the memory against program or erase operations. when the write protect signal is low the device does not accept program or erase operations, therefore, the contents of the memory array cannot be altered. the write protect signal is not latched by write enable to ensure protection, even during power-up. 4.6 standby the memory enters standby mode by driving chip enable, e , high. in standby mode, the device is deselected, outputs are disabled and power consumption is reduced. table 4. bus operations bus operation e al cl r w wp i/o0 - i/o7 command input v il v il v ih v ih rising x (1) command address input v il v ih v il v ih rising x address data input v il v il v il v ih rising v ih data input data output v il v il v il falling v ih x data output write protect x x x x x v il x standby v ih xxx xv il /v dd x 1. wp must be v ih when issuing a program or erase command. table 5. address insertion (1) bus cycle i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 1 st a7 a6 a5 a4 a3 a2 a1 a0 2 nd v il v il v il v il a11 a10 a9 a8 3 rd a19 a18 a17 a16 a15 a14 a13 a12 4 th a27 a26 a25 a24 a23 a22 a21 a20 5 th v il v il v il v il a31 (2) a30 a29 a28 1. any additional address input cycles will be ignored. 2. a31 is valid only for the nand16gw3c2a.
nand08gw3c2a, nand16 gw3c2a bus operations 19/58 table 6. address definitions address definition a0 - a11 column address a12 - a18 page address a19 - a31 block address
command set nand08gw3c2a, nand16gw3c2a 20/58 5 command set all bus write operations to the device are interpreted by the command interface. the commands are input on i/o0-i/o7 and are latched on the rising edge of write enable when the command latch enable signal is high. device operations are selected by writing specific commands to the command register. the two-step command sequences for program and erase operations are imposed to maximize data security. the commands are summarized in table 7: commands . table 7. commands command bus write operations (1) 1. the bus cycles are only shown fo r issuing the codes. the cycles required to input the addresses or input/output data are not shown. commands accepted during busy 1 st cycle 2 nd cycle 3 rd cycle 4 th cycle read 00h 30h ? ? random data output 05h e0h ? ? page program (sequential input default) 80h 10h ? ? multiplane page program 80h 11h 81h 10h random data input 85h ? ? ? block erase 60h d0h ? ? multiplane block erase 60h 60h d0h ? reset ffh ? ? ? ye s read electronic signature 90h ? ? ? read status register 70h ? ? ? ye s
nand08gw3c2a, nand16gw 3c2a device operations 21/58 6 device operations this section gives the details of the device operations. 6.1 read memory array at power-up the device defaults to read mode. to enter read mode from another mode the read command must be issued, see table 7: commands . once a read command is issued, subsequent consecutive read comm ands only require the confirm command code (30h). once a read command is issued, two types of operations are available: random read and page read. 6.2 random read each time the read command is issued, the first read is random-read. 6.3 page read after the first random read access, the page data (2112 bytes) is transferred to the page buffer in a time of t whbh (refer to ta b l e 2 1 for value). once the transfer is complete, the ready/busy signal goes high. the data can then be read out sequentially (from the selected column address to last column address) by pulsing the read enable signal. the device can output random data in a page, instead of the consecutive sequential data, by issuing a random data output command. the random data output command can be used to skip some data during a sequential data output. the sequential operation can be resumed by changing the column address of the next data to be output, to the address which follows the random data output command.the random data output command can be issued as many times as required within a page.
device operations nand0 8gw3c2a, nand16gw3c2a 22/58 figure 7. read operations 1. highest address depends on device density. cl e w al r i/o rb 00h ai11016 busy command code data output (sequentially) address input tblbh1 30h command code
nand08gw3c2a, nand16gw 3c2a device operations 23/58 figure 8. random data output 6.4 page program the page program operation is the standard operation to program data to the memory array. generally, data is programmed sequentially, however, the device does support random input within a page. the memory array is programmed by page, however, partial page programming is allowed where any number of bytes (1 to 2112) can be programmed. only one consecutive partial page program operation is allowed on the same page. after exceeding this a block erase command must be issued before any further program operations can take place in that page. i/o rb address inputs ai08658b data output busy tblbh1 (read busy time) 000h cmd code 30h address inputs data output 05h e0h 5 add cycles main area spare area col add 1,2 row add 1,2,3 cmd code cmd code cmd code 2add cycles main area spare area col add 1,2 r
device operations nand0 8gw3c2a, nand16gw3c2a 24/58 6.5 sequential input to input data sequentially the addresses must be sequential and remain in one block. for sequential input, each page program operation comprises five steps: 1. one bus cycle is required to set up the page program (sequential input) command (see ta bl e 7 ). 2. five bus cycles are then required to input the program address (refer to ta bl e 5 ). 3. the data is loaded into the data registers. 4. one bus cycle is required to issue the page program confirm command to start the p/e/r controller. the p/e/r only starts if the data has been loaded in step 3. 5. the p/e/r controller then programs the data into the array. 6.6 random data input during a sequential input operation, the next sequential address to be programmed can be replaced by a random address issuing a random data input command. the following two steps are required to issue the command: 1. one bus cycle is required to setup the random data input command (see ta b l e 7 ). 2. two bus cycles are then required to input the new column address (refer to ta bl e 5 ). random data input can be repeated as often as required in any given page. once the program operation has started the status register can be read using the read status register command. during program operations the status register only flags errors for bits set to ?1? that have not been successfully programmed to ?0?. during the program operation, only the read status register and reset commands are accepted; all other commands are ignored. once the program operation has completed, the p/e/r controller bit sr6 is set to ?1? and the ready/busy signal goes high. the device remains in read status register mode until another valid command is written to the command interface. figure 9. page program operation i/o rb address inputs sr0 ai08659 data input 10h 70h 80h page program setup code confirm code read status register busy tblbh2 (program busy time)
nand08gw3c2a, nand16gw 3c2a device operations 25/58 figure 10. random data input during sequential data input 6.7 multiplane page program the devices support multiplane page program, that allows the programming of two pages in parallel, one in each plane. a multiplane page program operation requires two steps: 1. the first step loads serially up to two pages of data (4224 bytes) into the data buffer. it requires: ? one clock cycle to set up the page program command (see section 6.5: sequential input ). ? five bus write cycles to input the first page address and data. the address of the first page must be within the first plane (a19 = 0). ? one bus write cycle to issue the page program confirm code. after this the device is busy for a time of t blbh5 . ? when the device returns to the ready state (ready/busy high), a multiplane page program setup code must be issued, followed by the second page address (5 write cycles) and data. the address of the second page must be within the second plane (a19=1), and a18 to a12 must be the address bits loaded during the first address insertion. i/o address inputs ai08664 data intput 80h cmd code address inputs data input 85h 5 add cycles main area spare area col add 1,2 row add 1,2,3 cmd code 2 add cycles main area spare area col add 1,2 rb busy tblbh2 (program busy time) sr0 10h 70h confirm code read status register
device operations nand0 8gw3c2a, nand16gw3c2a 26/58 2. the second step programs, in parallel, the two pages of data loaded into the data buffer into the appropriate memory pages. it is started by issuing a program confirm command. as for standard page program operations, the device supports random data input during both data loading phases. once the multiplane page program operation has started, maintaining a delay of t blbh5 , the status register can be read using the read status register command. once the multiplane page program operation has completed, the p/e/r controller bit sr6 is set to ?1? and the ready/busy signal goes high. if the multiplane page program fails, an error is signaled on bit sr0 of the status register. however, there is no way to identify for which page the program operation failed. see figure 11 for a description of multiplane page program waveforms. figure 11. multiplane page program 6.8 block erase erase operations are done one block at a time. an erase operation sets all of the bits in the addressed block to ?1?. all previous data in the block is lost. an erase operation consists of three steps (refer to figure 12 ): 1. one bus cycle is required to setup the block erase command. only addresses a19 to a31 are used; the other address inputs are ignored. 2. three bus cycles are then required to load the address of the block to be erased. refer to ta bl e 6 for the block addresses of each device. 3. one bus cycle is required to issue the block erase confirm command to start the p/e/r controller. the erase operation is initiated on the rising edge of write enable, w , after the confirm command is issued. the p/e/r controller handles block erase and implements the verify process. during the block erase operation, only the read status register and reset commands are accepted; all other commands are ignored. i/o rb address inputs ai13636 data input 11h 81h 80h page program setup code confirm code multiplane page program setup code busy tblbh5 a19=0 address inputs sr0 data input 10h 70h confirm code read status registe r a19=1 busy tblbh2 (program busy time)
nand08gw3c2a, nand16gw 3c2a device operations 27/58 once the program operation has completed, the p/e/r controller bit sr6 is set to ?1? and the ready/busy signal goes high. if the operation completes successfully, the write status bit sr0 is ?0?, otherwise it is set to ?1?. figure 12. block erase operation 6.9 multiplane block erase the multiplane block erase operation allows erasing two blocks in parallel, one in each plane. it consists of three steps (refer to figure 13: multiplane block erase operation ): 1. eight bus cycles are required to set up the block erase command and load the addresses of the blocks to be erased. the setup command, followed by the address of the block to be erased, must be issued for each block. no dummy busy time is required between the first and second block address insertion. as for multiplane page program, the address of the first and second page must be within the first plane (a19 = 0) and second plane (a19 = 1), respectively. 2. one bus cycle is then required to issue the multiplane block erase confirm command and start the p/e/r controller. if the multiplane block erase fails, an error is signaled on bit sr0 of the status register. however, there is no way to identify for which page the multiplane block erase operation failed. figure 13. multiplane block erase operation i/o rb block address inputs sr0 ai07593 d0h 70h 60h block erase setup code confirm code read status register busy tblbh3 (erase busy time) i/o rb block address inputs sr0 ai13637 d0h 70h 60h block erase setup code confirm code read status register busy tblbh3 (erase busy time) a19=0 block address inputs 60h block erase setup code a19=1
device operations nand0 8gw3c2a, nand16gw3c2a 28/58 6.10 reset the reset command is used to reset the command interface and status register. if the reset command is issued during any operation, the operation is aborted. if it is a program or erase operation that is being aborted, the contents of the memory locations being modified are no longer valid as the data is partially programmed or erased. if the device has already been reset, then the new reset command is not accepted. the ready/busy signal goes low for t blbh4 after the reset command is issued. the value of t blbh4 depends on the operation that the device was performing when the command was issued. refer to ta b l e 2 1 for the values. 6.11 read status register the device contains a status register that provides information on the current or previous program or erase operation. the various bits in the status register convey information and errors on the operation. the status register is read by issuing the read status register command. the status register information is present on the output data bus (i/o0-i/ o7) on the falling edge of chip enable or read enable, whichever occurs last. when several memories are connected in a system, the use of chip enable and read enab le signals allows the system to poll each device separately, even when the ready/busy pins are common-wired. it is not necessary to toggle the chip enable or read enable signals to update the contents of the status register. after the read status register command has been issued, the device remains in read status register mode until another command is is sued. therefore, if a read status register command is issued during a random read cycle a new read command must be issued to continue with a page read operation. refer to ta b l e 8 which summarizes status register bits and should be read in conjunction with the following text descriptions. 6.11.1 write protection bit (sr7) the write protection bit can identify if the device is protected or not. if the write protection bit is set to ?1? the device is not protected and pr ogram or erase operations are allowed. if the write protection bit is set to ?0? the device is protected and program or erase operations are not allowed. 6.11.2 p/e/r contro ller bit (sr6) status register bit sr6 acts as a p/e/r controller bit, which indicates whether the p/e/r controller is active or inactive. when the p/e/r controller bit is set to ?0?, the p/e/r controller is active (device is busy); when the bit is set to ?1?, the p/e/r controller is inactive (device is ready). 6.11.3 error bit (sr0) the error bit is used to identify if any errors have been detected by the p/e/r controller. the error bit is set to ?1? when a program or erase operation has failed to write the correct data to the memory. if the error bit is set to ?0?, the operation has completed successfully.
nand08gw3c2a, nand16gw 3c2a device operations 29/58 6.13 read electronic signature the device contains a manufacturer code and device code. the following three steps are required to read these codes: 1. one bus write cycle to issue the read electronic signature command (90h) 2. one bus write cycle to input the address (00h) 3. four bus read cycles to sequentially output the data (as shown in table 9: electronic signature ) 6.12 sr5, sr4, sr3, sr2 and sr 1 bits are reserved table 8. status register bits bit name logic level definition sr7 write protection ?1? not protected ?0? protected sr6 program/erase/read controller ?1? p/e/r c inactive, device ready ?0? p/e/r c active, device busy sr5, sr4, sr3, sr2, sr1 reserved don?t care sr0 generic error ?1? error ? operation failed ?0? no error ? operation successful table 9. electronic signature part number byte/word 1 byte/word 2 byte 3 (see table 10 ) byte 4 (see table 11 ) byte 5 (see table 12 ) manufacturer code device code nand08gw3c2a 20h d3h 14h a5h 6ch nand16gw3c2a (1) 1. each 8-gbit die returns its own electronic signature.
device operations nand0 8gw3c2a, nand16gw3c2a 30/58 table 10. electronic signature byte 3 i/o definition value description i/o1-i/o0 internal chip number 0 0 0 1 1 0 1 1 1 2 4 8 i/o3-i/o2 cell type 0 0 0 1 1 0 1 1 2-level cell 4-level cell 8-level cell 16-level cell i/o5-i/o4 number of simultaneously programmed pages 0 0 0 1 1 0 1 1 1 2 4 8 i/o6 interleaved programming between multiple devices 0 1 not supported supported i/o7 cache program 0 1 not supported supported table 11. electronic signature byte 4 i/o definition value description i/o1-i/o0 page size (without spare area) 0 0 0 1 1 0 1 1 1 kbytes 2 kbytes 4 kbytes 8 kbytes i/o2 spare area size (byte/512 byte) 0 1 8 16 i/o7, i/o3 minimum sequential access time 0 0 1 0 0 1 1 1 30/50 ns 25 ns reserved reserved i/o5-i/o4 block size (without spare area) 0 0 0 1 1 0 1 1 64 kbytes 128 kbytes 256 kbytes 512 kbytes i/o6 organization 0 1 x8 x16
nand08gw3c2a, nand16gw 3c2a device operations 31/58 table 12. electronic signature byte 5 i/o definition value description i/o1 - i/o0 reserved 0 0 i/o3 - i/o2 plane number 0 0 0 1 1 0 1 1 1 plane 2 planes 4 planes 8 planes i/o6 - i/o4 plane size (without spare area) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 64 mbits 128 mbits 256 mbits 512 mbits 1 gb 2 gb 4 gb 8 gb i/o7 reserved 0
concurrent operations and ers on the nand16gw3c2a nand08gw3c2a, nand16gw3c2a 32/58 7 concurrent operations and ers on the nand16gw3c2a the nand16gw3c2a is composed by two 8-gbit dice stacked together. this configuration allows the device to support concurrent operations. this means that while performing an operation in one die (erase, read, program, etc.), another operation is possible in the other die. the standard read status register (ers) operation returns the status of the nand16gw3c2a device. to provide informat ion on each 8-gbit die, the nand16gw3c2a features an extended read status register command that allows to check independently the status of each die. the following steps are required to perform concurrent operations: 1. select one of the two dice by setting the most significant address bit a31 to ?0? or ?1?. 2. execute one operation on this die. 3. launch a concurrent operation on the other die. 4. check the status of these operations by performing an extended read status register operation. all combinations of operations are possible except executing read on both dice. this is due to the fact that the input/output bus is common to both dice. refer to ta b l e 1 3 for the description of the extended read status register command sequence, and to ta b l e 8 . for the definition of the status register bits. table 13. extended read status register commands command address range 1 bus write cycle read 1st die status address 0x7fffffff f1h read 2nd die status 0x7fffffff < address 0xfffffff f2h
nand08gw3c2a, nand16gw 3c2a data protection 33/58 8 data protection the device has hardware features to protect against program and erase operations. it features a write protect, wp , pin, which protects the device against program and erase operations. it is recommended to keep wp at v il during power-up and power-down. 9 software algorithms this section gives information on the software algorithms that numonyx recommends implementing to manage the bad blocks and extend the lifetime of the nand device. nand flash memories are programmed and erased by fowler-nordheim tunneling using high voltage. exposing the device to high voltage for extended periods can cause the oxide layer to be damaged. for this reason, the number of program and erase cycles is limited (see ta b l e 1 5 for value). it is recommended to implement garbage collection, wear-leveling and error correction code algorithms to extend the number of program and erase cycles and to increase data retention. to help integrate a nand memory into an ap plication numonyx can provide a file system os native reference software, which supports the basic commands of file management. contact the nearest numonyx sales office for more details. 9.1 bad block management devices with bad blocks have the same quality level and the same ac and dc characteristics as devices where all the blocks are valid. a bad block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor. the devices are supplied with all the locations inside valid blocks erased (ffh). the bad block information is written prior to shipping. any block, where the 1st byte in the spare area of the last page, does not contain ffh, is a bad block. the bad block information must be read before any erase is attempted as the bad block information may be erased. for the system to be able to recognize the bad blocks based on the original information it is recommended to create a bad block table following the flowchart shown in figure 14.
software algorithms nand0 8gw3c2a, nand16gw3c2a 34/58 9.2 nand flash memory failure modes the nand08gw3c2a and nand16gw3c2a devices may contain bad blocks, where the reliability of blocks that contai n one or more invalid bits is not guaranteed. additional bad blocks may develop during the lifetime of the device. to implement a highly reliable system, all the possible failure modes must be considered: program/erase failure in this case, the block has to be replaced by copying the data to a valid block. these additional bad blocks can be identified as attempts to program or erase them and will give errors in the status register. because the failure of a page program operation does not affect the data in other pages in the same block, the block can be replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. the copy back program command can be used to copy the data to a valid block. see section figure 10.: random data input during sequential data input for more details. read failure in this case, ecc correction must be implemented. to efficiently use the memory space, it is recommended to recover single-bit errors in read by ecc, without replacing the whole block. refer to ta b l e 1 4 for the procedure to follow if an error occurs during an operation. table 14. block failure operation procedure erase block replacement program block replacement or ecc (with 4 bit/528 byte) read ecc (with 4 bit/528 byte)
nand08gw3c2a, nand16gw3c 2a software algorithms 35/58 figure 14. bad block management flowchart 9.3 garbage collection when a data page needs to be modified, it is faster to write to the first available page and mark the previous page as invalid. after several updates it is necessary to remove invalid pages to free some memory space. to free this memory space and allow further program operations, it is recommended to implement a garbage collection algorithm. in a garbage collection software the valid pages are copied into a free area and the block containing the invalid pages is erased (see figure 15 ). figure 15. garbage collection ai07588c start end no yes yes no block address = block 0 data = ffh? last block? increment block address update bad block table valid page invalid page free page (erased) old area ai07599b new area (after gc)
software algorithms nand0 8gw3c2a, nand16gw3c2a 36/58 9.4 wear-leveling algorithm for write-intensive applications, it is recommended to implement a wear-leveling algorithm to monitor and spread the number of write cycles per block. in memories that do not use a wear-leveling algorithm, not all blocks get used at the same rate. the wear-leveling algorithm ensures that equal use is made of all the available write cycles for each block. there are two wear-leveling levels: 1. first level wear-leveling, where new data is programmed to the free blocks that have had the fewest write cycles 2. second level wear-leveling, where long-lived data is copied to another block so that the original block can be used for more frequently changed data. the second level wear-leveling is triggered when the difference between the maximum and the minimum number of write cycles per block reaches a specific threshold.
nand08gw3c2a, nand16gw3c 2a software algorithms 37/58 9.5 hardware simulation models 9.5.1 behavioral simulation models denali software corporation models are platform-independent functional models designed to assist customers in perfor ming entire system simulations (typical vhdl/verilog). these models describe the logic behavior and timing s of nand flash devices, and, therefore, allow software to be developed before hardware. 9.5.2 ibis simulations models i/o buffer information specification (ibis) models describe the behavior of the i/o buffers and electrical characteristics of flash devices. these models provide information such as ac characteristics, rise/fall times, and package mechanical data, all of which are measured or simulated at voltage and temperature ranges wider than those allowed by target specifications. ibis models are used to simu late pcb connections and can be used to resolve compatibility issues when upgrading devices. they can be imported into spicetools.
program and erase times and endurance cycles nand08gw3c2a, nand16gw3c2a 38/58 10 program and erase times and endurance cycles table 15 shows the program and erase times and th e number of program/erase cycles per block. table 15. program and erase times and program erase endurance cycles parameters nand08gw3c2a, nand16gw3c2a unit min typ max page program time 800 2000 s block erase time 2.5 3ms program/erase cycles ( per block (with ecc )10,000 cycles data retention 10 years
nand08gw3c2a, nand16 gw3c2a maximum ratings 39/58 11 maximum ratings stressing the device above the ratings listed in table 16: absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliabilit y. refer also to the numonyx sure program and other relevant quality documents. table 16. absolute maximum ratings symbol parameter value unit min max t bias temperature under bias ? 50 125 c t stg storage temperature ? 65 150 c v io (1) 1. minimum voltage may undershoot to ?2 v for less t han 20 ns during transitions on input and i/o pins. maximum voltage may overshoot to v dd + 2 v for less than 20 ns dur ing transitions on i/o pins. input or output voltage ? 0.6 4.6 v v dd supply voltage ? 0.6 4.6 v
dc and ac parameters nand08gw3c2a, nand16gw3c2a 40/58 12 dc and ac parameters this section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristics tables are derived from tests performed under the measurement conditions summarized in table 17: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match th e measurement conditions when relying on the quoted parameters. table 17. operating and ac measurement conditions parameter nand08gw3c2a, nand16gw3c2a units min max supply voltage (v dd )2.7 3.6v ambient temperature (t a ) 0 70 c ?40 85 c load capacitance (c l ) (1 ttl gate and c l )50pf input pulses voltages 0.4 2.4 v input and output timing ref. voltages 1.5 v output circuit resistor r ref 8.35 k ? input rise and fall times 5 ns table 18. capacitance (1) 1. t a = 25 c, f = 1 mhz. c in and c i/o are not 100% tested. symbol parameter test condition typ max unit c in input capacitance v in = 0 v 10 pf c i/o input/output capacitance v il = 0 v 10 pf
nand08gw3c2a, nand16gw3c 2a dc and ac parameters 41/58 table 19. dc characteristics symbol parameter test conditions min typ max unit i dd1 operating current sequential read t rlrl minimum e =v il, i out = 0 ma -1530ma i dd2 program - - 15 30 ma i dd3 erase - - 15 30 ma i dd4 standby current (ttl) e=v ih , wp =0/v dd 1 ma i dd5 standby current (cmos) e =v dd -0.2, wp =0/v dd - 10 50 a i li input leakage current v in = 0 to 3.6v - - 10 a i lo output leakage current v out = 0 to 3.6v - - 10 a v ih input high voltage - 2.0 - v dd +0.3 v v il input low voltage - -0.3 - 0.8 v v oh output high voltage level i oh = -400a 2.4 - - v v ol output low voltage level i ol = 2.1ma - - 0.4 v i ol (rb ) output low current (rb ) v ol = 0.4v 8 10 ma
dc and ac parameters nand08gw3c2a, nand16gw3c2a 42/58 table 20. ac characteristics for command, address, data input symbol alt. symbol parameter value unit t allwh t als address latch low to write enable high al setup time min 12 ns t alhwh address latch high to write enable high t clhwh t cls command latch high to write enable high cl setup time min 12 ns t cllwh command latch low to write enable high t dvwh t ds data valid to write enable high data setup time min 12 ns t elwh t cs chip enable low to write enable high e setup time min 20 ns t whalh t alh write enable high to address latch high al hold time min 5 ns t whall write enable high to address latch low t whclh t clh write enable high to command latch high cl hold time min 5 ns t whcll write enable high to command latch low t whdx t dh write enable high to data transition data hold time min 5 ns t wheh t ch write enable high to chip enable high e hold time min 5 ns t whwl t wh write enable high to write enable low w high hold time min 10 ns t wlwh t wp write enable low to write enable high w pulse width min 12 ns t wlwl t wc write enable low to write enable low write cycle time min 25 ns
nand08gw3c2a, nand16gw3c 2a dc and ac parameters 43/58 table 21. ac characteristics for operations symbol alt. symbol parameter value unit min typ max t allrl1 t ar address latch low to read enable low read electronic signature 10 ns t allrl2 read cycle 10 ns t bhrl t rr ready/busy high to read enable low 20 ns t blbh1 ready/busy low to ready/busy high read busy time 60 s t blbh2 t prog program busy time 2000 s t blbh3 t bers erase busy time 3 ms t blbh4 t rst reset busy time, during ready 5 s reset busy time, during read 5 s reset busy time, during program 10 s reset busy time, during erase 500 s t blbh5 t cbsy dummy busy time for multiplane operations 1 2 s t cllrl t clr command latch low to read enable low 10 ns t dzrl t ir data hi-z to read enable low 0 ns t ehqz t chz chip enable high to output hi-z 30 ns t elqv t cea chip enable low to output valid 25 ns t rhrl t reh read enable high to read enable low read enable high hold time 10 ns t ehqx t coh chip enable high to output hold 15 ns t rhqx t rhoh read enable high to output hold 15 ns t rlqx t rloh read enable low to output hold (edo mode) 5 ns t rhqz t rhz read enable high to output hi-z 100 ns t rlrh t rp read enable low to read enable high read enable pulse width 12 ns t rlrl t rc read enable low to read enable low read cycle time 25 ns t rlqv t rea read enable low to output valid read enable access time 20 ns read es access time (1) t whbh t r write enable high to ready/busy high read busy time 60 s t whbl t wb write enable high to ready/busy low 100 ns t whrl t whr write enable high to read enable low 80 ns t whwh (2) t adl last address latched on data loading time during program operations 70 ns t vhwh (3) t ww write protection time 100 ns t vlwh (3) 100 ns 1. es = electronic signature. 2. t whwh is the delay from write enable risi ng edge during the final address cycle to write enable rising edge during the first data cycle. 3. wp high to w high during program/erase enable operations.
dc and ac parameters nand08gw3c2a, nand16gw3c2a 44/58 figure 16. command latch ac waveforms figure 17. address latch ac waveforms ai12470b cl e w al i/o tclhwh telwh twhcll twheh twlwh tallwh twhalh command tdvwh twhdx (cl setup time) (cl hold time) (data setup time) (data hold time) (alsetup time) (al hold time) h(e setup time) (e hold time) ai12471 cl e w al i/o twlwh telwh twlwl tcllwh twhwl talhwh tdvwh twlwl twlwl twlwh twlwh twlwh twhwl twhwl twhdx twhall tdvwh twhdx tdvwh twhdx tdvwh twhdx twhall adrress cycle 1 twhall (al setup time) (al hold time) adrress cycle 4 adrress cycle 3 adrress cycle 2 (cl setup time) (data setup time) (data hold time) (e setup time) adrress cycle 5 twlwl twlwh tdvwh twhdx twhwl twhall
nand08gw3c2a, nand16gw3c 2a dc and ac parameters 45/58 figure 18. data input latch ac waveforms 1. the last data input is the 2112th. figure 19. sequential data output after read ac waveforms 1. cl = low, al = low, w = high. 2. t rhqx is applicable for frequencies lower than 33 mhz (i.e. t rlrl higher than 30 ns). twhclh cl e al w i/o tallwh twlwl twlwh twheh twlwh twlwh data in 0 data in 1 data in last tdvwh twhdx tdvwh twhdx tdvwh twhdx ai12472 (data setup time) (data hold time) (alsetup time) (cl hold time) (e hold time) e ai13174 r i/o rb trlrl trlqv trhrl trlqv data out data out data out trhqz tbhrl trlqv trhqz tehqz (read cycle time) (r accesstime) (r high holdtime) tehqx trhqx (2)
dc and ac parameters nand08gw3c2a, nand16gw3c2a 46/58 figure 20. sequential data output after read ac waveforms (edo mode) 1. in edo mode, cl and al are low, v il , and w is high, v ih . 2. t rlqx is applicable for frequencies higher than 33 mhz (i.e. t rlrl lower than 30 ns). figure 21. read status register ac waveform e ai13175 r i/o rb trlrl trlqv trhrl trlqv data out data out data out tbhrl trhqz tehqz (r accesstime) tehqx trhqx (2) trlrh telqv trlqx telwh tdvwh status register output 70h or 7bh cl e w r i/o tclhwh twhdx twlwh twhcll tcllrl tdzrl trlqv tehqx trhqx twhrl telqv twheh ai13177 (data setup time) (data hold time) tehqz trhqz
nand08gw3c2a, nand16gw3c 2a dc and ac parameters 47/58 figure 22. read electronic signature ac waveform 1. refer to table 9 for the values of the manufacturer and device codes, and to table 10 , table 11 , and table 12 for the information contained in byte 3, byte 4, and byte 5. 90h 00h man. code device code cl e w al r i/o trlqv read electronic signature command 1st cycle address ai13178 (read es access time) tallrl1 byte4 byte3 byte1 byte2 see note.1 byte5
dc and ac parameters nand08gw3c2a, nand16gw3c2a 48/58 figure 23. page read operation ac waveform cl e w al r i/o rb twlwl twhbl tallrl2 00h data n data n+1 data n+2 data last twhbh trlrl tehqz trhqz ai13638 busy command code address n input data output from address n to last byte or word in page add.n cycle 1 add.n cycle 4 add.n cycle 3 add.n cycle 2 (read cycle time) trlrh tblbh1 30h add.n cycle 5
nand08gw3c2a, nand16gw3c 2a dc and ac parameters 49/58 figure 24. page program ac waveform cl e w al r i/o rb sr0 ai13639 n last 10h 70h 80h page program setup code confirm code read status register twlwl twlwl twlwl twhbl tblbh2 page program address input data input add.n cycle 1 add.n cycle 4 add.n cycle 3 add.n cycle 2 (write cycle time) (program busy time) add.n cycle 5 twhwh
dc and ac parameters nand08gw3c2a, nand16gw3c2a 50/58 figure 25. block erase ac waveform figure 26. reset ac waveform d0h 60h sr0 70h ai08038c twhbl twlwl tblbh3 block erase setup command block erase cl e w al r i/o rb confirm code read status register block address input (erase busy time) (write cycle time) add. cycle 1 add. cycle 3 add. cycle 2 w r i/o rb tblbh4 al cl ffh ai08043 (reset busy time)
nand08gw3c2a, nand16gw3c 2a dc and ac parameters 51/58 figure 27. program/erase enable waveform figure 28. program/erase disable waveform w rb tvhwh ai12477 wp i/o 80h 10h w rb tvlwh ai12478 wp i/o 80h 10h high
dc and ac parameters nand08gw3c2a, nand16gw3c2a 52/58 12.1 ready/busy signal electrical characteristics figure 30 , figure 29 and figure 31 show the electrical charac teristics for the ready/busy signal. the value required for the resistor r p can be calculated using the following equation: so, where i l is the sum of the input currents of all the devices tied to the ready/busy signal. r p max is determined by the maximum value of t r . figure 29. ready/busy ac waveform figure 30. ready/busy load circuit r p min v ddmax v olmax ? () i ol i l + ------------------------------------------------------------- = r p min 3.2v 8ma i l + --------------------------- = ai07564b busy v oh ready v dd v ol t f t r ai07563b r p v dd v ss rb device open drain output ibusy
nand08gw3c2a, nand16gw3c 2a dc and ac parameters 53/58 figure 31. resistor value versus waveform timings for ready/busy signal 1. t = 25c. 12.2 data protection the numonyx nand device is designed to guarantee data protection during power transitions. a v dd detection circuit disables all nand operations, if v dd is below the v lko threshold. in the v dd range from v lko to the lower limit of nominal range, the wp pin should be kept low (v il ) to guarantee hardware protection during power transitions as shown in figure 32. figure 32. data protection a t r t f ibusy r p (k ?) 12 34 50 150 100 1 2 3 ibusy (ma) 2.4 1.2 0.8 0.6 50 100 150 200 1.8 1.8 1.8 1.8 0 200 4 v dd = 3.3 v, c l = 50 pf t r , t f (ns) ai11086 v lko v dd w nominal range locked locked
package mechanical nand0 8gw3c2a, nand16gw3c2a 54/58 13 package mechanical this section contains mechanical data for the packages. figure 33. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline 1. drawing is not to scale. tsop-g b e die c l a1 e1 e a a2 1 24 48 25 d1 l1 cp table 22. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.100 0.050 0.150 0.0039 0.0020 0.0059 a2 1.000 0.950 1.050 0.0394 0.0374 0.0413 b 0.220 0.170 0.270 0.0087 0.0067 0.0106 c 0.100 0.210 0.0039 0.0083 cp 0.080 0.0031 d1 12.000 11.900 12.100 0.4724 0.4685 0.4764 e 20.000 19.800 20.200 0.7874 0.7795 0.7953 e1 18.400 18.300 18.500 0.7244 0.7205 0.7283 e 0.500 ? ? 0.0197 ? l 0.600 0.500 0.700 0.0236 0.0197 0.0276 l1 0.800 0.0315 a 305305
nand08gw3c2a, nand16gw 3c2a package mechanical 55/58 figure 34. lga52 12 x 17 mm, 1 mm pitch , package outline e1 e2 d1 d2 eb2 lga-9g ball "a1" e d b1 e ee1 a2 a ddd fd fd1 fe fe1 table 23. lga52 12 x 17 mm, 1 mm pitch , package mechanical data symbol millimeters inches typ min max typ min max a 0.650 0.0256 a2 0.650 0.0256 b1 0.700 0.650 0.750 0.0276 0.0256 0.0295 b2 1.000 0.950 1.050 0.0394 0.0374 0.0413 d 12.000 11.900 12.100 0.4724 0.4685 0.4764 d1 6.000 0.2362 d2 10.000 0.3937 ddd 0.100 0.0039 e 17.000 16.900 17.100 0.6693 0.6654 0.6732 e1 12.000 0.4724 e2 13.000 0.5118 e 1.000 ? ? 0.0394 ? ? ee1 2.000 ? ? 0.0787 ? ? fd 3.000 0.1181 fd1 1.000 0.0394 fe 2.500 0.0984 fe1 2.000 0.0787
ordering information nand0 8gw3c2a, nand16gw3c2a 56/58 14 ordering information devices are shipped from the factory with the memory content bits, in valid blocks, erased to ?1?. for further information on any aspect of this device, please contact your nearest numonyx sales office. table 24. ordering information scheme example: nand08g w 3 c 2 a n 1 e device type nand flash memory density 08g = 8 gbits 16g = 16 gbits operating voltage w = v dd = 2.7 to 3.6 v bus width 3 = x 8 family identifier c = 2112 bytes page mlc device options 2 = chip enable don't care enabled 4 = chip enable don't care enabled with 2 chip enable and 2 ready/busy signals product version a = first version package n = tsop48 12 x 20 mm zl = ulga52 12 x 17 mm temperature range 1 = 0 to 70 c 6 = ? 40 to 85 c option e = ecopack? package, standard packing f = ecopack? package, tape & reel packing
nand08gw3c2a, nand16gw3c2a revision history 57/58 15 revision history table 25. document revision history date revision changes 22-dec-2006 0.1 initial release. 11-jun-2007 1 ? changed throughout the document "nand16gw3c2a" to "nand16gw3c4a. ? listed throughout document the details relating to the two 8-gbit dice, the two chip enable, and two ready/busy signals in the nand16gz3c4a, which required changes in several figures and tables. ? added power-up and power-down minimum recovery time information in section 3.8: ready/busy (rb1, rb2) . ? added program and read information in section table 14.: block failure . ? modified page program time param eters and program/erase cycles parameters in section table 15.: program and erase times and program erase endurance cycles . ? modified ac characteristics in section table 21.: ac characteristics for operations . 04-jan-2008 2 applied numonyx branding.
nand08gw3c2a, nand16gw3c2a 58/58 please read carefully: information in this document is provided in connection with numonyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties re lating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in n uclear facility applications. numonyx may make changes to specifications and product descriptions at any time, without notice. numonyx, b.v. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights th at relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting numonyx's website at http://www.numonyx.com . numonyx strataflash is a trademark or registered trademark of numonyx or its subsidiaries in the united states and other countr ies. *other names and brands may be claimed as the property of others. copyright ? 11/5/7, numonyx b.v. all rights reserved.

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